Memory that can be rapidly accessed is essential to the operation of any digital data processing device and programmed digital logic circuits. The data storage requirements can often be quite large since separate storage is often required for input data, operands and/or results of logic operations in addition to the program which provides control of the logic circuits for operating on the digital data. Accordingly, many types of memory devices have been developed to answer many different requirements in regard to trade-offs between access time, cost and required storage capacity.
Dynamic random access memories (DRAMs) are often the memory device type of choice where access time is moderate but low cost and very large storage capacity are of paramount importance. Such devices usually use only a single transistor for access to any given memory cell and store data as charge in a capacitor which can be selectively accessed by control of that single transistor. Many different technologies have been developed to enhance the integration density of such memories until many megabytes of storage may be formed on a single semiconductor chip of modest area. Access time is generally quite rapid but can be slowed during a “worst-case” access time by the need to periodically refresh the charge stored in the memory cells because of necessarily finite levels of charge leakage through the access transistors and other potential leakage paths and, for any access, by the response time of sense amplifiers. Such sense amplifiers which must react to whatever charge may remain in a storage capacitor (often referred to, for generality, as a storage node) at the time the memory cell is accessed are initially brought to a balanced, metastable state and then imbalanced by the voltage due to the charge or lack thereof stored in the storage node when the storage node is connected to a sense amplifier input; causing the sense amplifier to assume one of two stable states in accordance with the charge (or lack thereof) representing the stored data. It should be appreciated that the time required for a sense amplifier to assume a stable state and the likelihood that the correct stable state will be assumed can both be compromised by reduction in remaining stored charge due to leakage for a given refresh cycle frequency while increased refresh frequency and duration reduces the periods during which the memory (or particular portion of the memory) can be accessed. Errors and increases in sense amplifier response time can also be caused by alteration of stored charge due to impingement on a memory cell transistor, capacitor and/or conductor by alpha particles that cause ionization and thus produce electrical charge.
Additionally, a limitation on potential integration density of DRAMs is limitation on the design and location of access transistors imposed by the technology used to form the storage capacitors. For example, integration density can be increased if the access transistor can be placed above the storage node. However, preferred so-called deep trench (DT) capacitors which require etching a trench, lining the trench with a capacitor dielectric (e.g. oxide) and then filling the trench with polysilicon or other semiconductor material has necessarily limited the designs of transistors and the quality of semiconductor that can be provided for their formation above a storage node formed in such a manner.